﻿@inproceedings{
HLS:Latch96,
   Author = {Lin, Y. and Wu, T.},
   Title = {Storage optimization by replacing some flip-flops with latches},
   BookTitle = {Euro-DAC },
      Year = {1996} }

@inproceedings{
misc:Mul,
   Author = {Carl Lemonds},
   Title = {A High Throughput 16 by 16 Bit Multiplier for DSP Cores},
   BookTitle = {IEEE International Symposium on Circuits and Systems},
      Year = {1996} }

@inproceedings{
HLS:Latch01,
   Author = {W. Yang and I. Park and C. Kyung},
   Title = {Low-power high-level synthesis using latches},
   BookTitle = {ASP-DAC},
   Year = {2001} }

@book{
mc-book,
   Author = {C. Jacoboni and P. Lugli},
   Title = {The Monte Carlo Method for Semiconductor Device Simulation },
   Publisher = {Springer},
      Year = {1990} }

@misc{
URL:VX,
    author = {Synopsys},
    title = {PrimeTime {VX}},
    howpublished = "\url{http://www.synopsys.com/products/analysis/primetime_ds.html}"
}

@inproceedings{
HLS:Yibo09,
    author = {Y. Chen and Y. Xie},
    title = {Tolerating Process Variations in High-Level Synthesis Using Transparent Latches},
    booktitle = {ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Mentor09,
    author = {F. Wang and A. Takach and Y. Xie},
    title = {Variation-Aware Resource Sharing and Binding in Behavioral Synthesis},
    booktitle = {ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Greg09,
    author = {G. Lucas and S. Cromar and D. Chen},
    title = {{FastYield}: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization},
    booktitle = {ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Jung07,
    author = {J. Jung and T. Kim},
    title = {Timing Variation-Aware High Level Synthesis},
    booktitle = {ICCAD},
    year = {2007}
}

@inproceedings{
HLS:Wang08,
    author = {F. Wang and G. Sun and Y. Xie},
    title = {A Variation Aware High Level Synthesis Framework},
    booktitle = {DATE},
    year = {2008}
}

@inproceedings{
HLS:Wang082,
    author = {F. Wang and X. Wu and Y. Xie},
    title = {Variability-driven module selection with joint design time optimization and post-silicon tuning},
    booktitle = {ASPDAC},
    year = {2008}
}

@misc{
URL:freepdk,
    author = {NCSU},
    title = {45nm {FreePDK}},
    howpublished = "\url{http://www.eda.ncsu.edu/wiki/FreePDK}"
}

@inproceedings{
HLS:Khouri02,
    author = {K. Khouri and N. Jha},
    title = {Leakage power analysis and reduction during behavioral synthesis},
    booktitle = {IEEE Transaction on VLSI},
    year = {2002}
}

@inproceedings{
HLS:Tang05,
    author = {X. Tang and H. Zhou and P. Banerjee},
    title = {Leakage power optimization with dual-{Vth} libraray in high-level synthesis},
    booktitle = {DAC},
    year = {2005}
}

@inproceedings{
HLS:Mohanty07,
    author = {S.P. Mohanty and E. Kougianos},
    title = {Simultaneous power fluctuation and average power minimization during nano-{CMOS} behavioral synthesis},
    booktitle = {VLSID},
    year = {2007}
}

@inproceedings{
HLS:Srivastava07,
    author = {A. Srivastava and T. Kachru and D. Sylvester},
    title = {Low-power-design space exploration considering process variation using robust optimization},
    booktitle = {IEEE TCAD},
    year = {2007}
}

@inproceedings{
HLS:Srivastava04,
    author = {A. Srivastava and D. Sylvester},
    title = {Minimizing total power by simultaneous {Vdd-Vth} assignment},
    booktitle = {IEEE TCAD},
    year = {2004}
}

@inproceedings{
HLS:Kim03,
    author = {N. Kim and et al.},
    title = {Leakage current: {Moore's Law} meets static power},
    booktitle = {IEEE Computer},
    year = {2003}
}

@inproceedings{
HLS:Kulkarni04,
    author = {S. Kulkarni and A. Srivastava and D. Sylvester},
    title = {A new algorithm for improved {Vdd} assignment in low power dual {Vdd} systems},
    booktitle = {ISLPED},
    year = {2004}
}

@inproceedings{
HLS:Tawfik07,
    author = {S. Tawfik and V. Kursun},
    title = { Multi-{Vth} Level Conversion Circuits for Multi-{VDD} Systems},
    booktitle = {ISCAS},
    year = {2007}
}

@book{
op-book,
   Author = {E. Aarts and J. K. Lenstra},
   Title = {Local Search in Combinatorial Optimization},
   Publisher = {Princeton University Press},
      Year = {2003}
}

@inproceedings{
HLS:Raghunathan95,
    author = {Raghunathan, A. and Jha, N.K.},
    title = { An iterative improvement algorithm for low power data pathsynthesis},
    booktitle = {ICCAD},
    year = {1995}
}

@inproceedings{
HLS:Wolfgang09,
    author = {W. Rosenstiel},
    title = {Automated Synthesis and Verification of Embedded Systems: Wishful Thinking or Reality?},
    booktitle = {in Proceedings of ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Intel08,
    author = {C. Kenyon and et. al},
    title = {Managing Process Variation in {Intel's 45nm {CMOS} Technology}},
    booktitle = {Intel Technology Journal},
    year = {June 2008}
}

@inproceedings{
HLS:SOCC08,
    author = {Y. Chen and Y. Xie},
    title = {{ILP}-based Scheme for Timing Variation-aware Scheduling and Resource Binding},
    booktitle = {Proc. of SOCC Conference},
    year = {2008}
}


@book{
hls-newbook,
   Author = {P. Coussy and A. Morawiec},
   Title = {High-level synthesis: from algorithm to digital circuit},
   Publisher = {Springer},
      Year = {2008}
}

@inproceedings{ xie:iccad06,
   Author = {Hung, W.-L. and Wu, X. and Xie, Y.},
   Title = {Guarantee performance yield in high level synthesis},
   BookTitle = {International Conference on Computer Aided Design},
      Year = {2006} }
